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DS2433
AC ELECTRICAL CHARACTERISTICS—OVERDRIVE SPEED
( T A = -40 ? C to +85 ? C. )
PARAMETER
Time Slot
Write 1 Low Time
Write 0 Low Time
Read Low Time
Read Data Valid
Release Time
Read Data Setup
SYMBOL
t SLOT
t LOW1
t LOW0
t LOWR
t RDV
t RELEASE
t SU
MIN
6
1
6
1
0
TYP
2
1.5
MAX
16
2
16
2
4
1
UNITS
? s
? s
? s
? s
? s
? s
? s
NOTES
8
8
9
10
Recovery Time
t REC
1
? s
Reset Time High
t RSTH
48
? s
11
Reset Time Low
Presence Detect High
Presence Detect Low
t RSTL
t PDHIGH
t PDLOW
48
2
8
80
6
24
? s
? s
? s
NOTES:
1)
2)
3)
4)
5)
V PUP = external pullup voltage. See Figure 8.
All voltages are referenced to ground.
V IH is a function of the external pullup resistor and V PUP .
Input load is to ground.
The Copy Scratchpad takes 5ms maximum during which the voltage on the 1-Wire bus must not fall
below 2.8V.
6) Capacitance on the data pin could be 800pF when power is first applied. If a 5k ?? resistor is used to
pull up the data line to V PUP , 5 ? s after power has been applied the parasite capacitance will not affect
normal communications.
7) During the execution of the Copy Scratchpad command the DS2433 automatically erases the memory
locations to be written to. No extra steps need to be taken by the bus master.
8) The duration of the low pulse sent by the master should be a minimum of 1 μ s with a maximum value
as short as possible to allow time for the pullup resistor to recover the line to a high level before the
1-Wire device samples in the case of a write-one time or before the master samples in the case of a
read-one time.
9) The optimal sampling point for the master is as close as possible to the end time of the t RDV period
without exceeding t RDV . For the case of a read-one time slot, this maximizes the amount of time for
the pullup resistor to recover to a high level. For a read-zero time slot, it ensures that a read will occur
before the fastest device(s) release the line.
10) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 ? s of this falling edge.
11) An additional reset or communication sequence cannot begin until the reset high time has expired.
12) The reset low time (t RSTL ) should be restricted to a maximum of 960 ? s, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
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